1. Field of the Invention
This invention relates generally to the field of digital clock generation and, more particularly, to a high-speed counter circuit with a partially-syncronous operation which conserves power.
2. Description of the Related Art
Syncronously clocked logic operations are considered by many to be the preferred method of processing high-speed precision signals. As used herein, syncronous counters are defined as circuits that are clocked with a high speed reference clock that is at least as fast as the signal being processed. In a multi-stage divider, the original input signal whose frequency is being divided can be used as the reference clock, for example. Thus, syncronous circuitry operates at relatively high speeds, and relatively large amounts of power are required to process signals with precision (without large propagation delays) at high speeds. Further, conventional syncronous processing requires additional support circuitry. In a counter, for example, gates must be added between each flip-flop to syncronously compare the outputs of each stage of division. The circuitry needed to support the flip-flop dividers also uses power.
Asyncronous processing, such as counters used in the division of an input signal, are also operated with respect to a reference clock which is the output signal of previous stages. Thus, the overall speed of operation is reduced at every stage of division. Lower operation speeds typically mean that propagation delays are less of a concern and the parts can be operated at lower power levels
It would be advantageous if precision, high-speed, circuits could be designed with at least some asyncronous components to reduce the amount of power consumed.
It would be advantageous if precision, high-speed, circuits could be devised that combined the use of synchronous and asyncronous components to use less power than a conventional syncronous counter.
It would be advantageous if precision, high-speed, circuits could be devised to reduce power consumption even when syncronous design principles are adhered to. To that end, it would be advantageous if a non-integer synchronous counter could be desired which operated at lower power consumption levels.
Accordingly, an integrated circuit partially-syncronous counter is provided comprising synchronous and asyncronous counters, as well a load circuit to manage the cooperation between the two counter sections. A high-speed counter section accepts a reference clock signal, divisor commands, and a load pulse. The high-speed counter syncronously divides the reference clock signal, in response to the load pulse, with a selectable divisor responsive to divisor commands. A low-speed counter section asyncronously divides the high-speed counter signal by a fixed value to provide low-speed counter signals.
The load circuit supplies a load pulse that is responsive to the low-speed counter signal, high-speed counter signals, and the reference clock signals. The load pulse is used to periodically reinitialize the high-speed counter. Upon reinitialization, the values of the divisor commands are loaded and used to offset the high-speed counter signals, which in effect causes the reference clock signals to be divided by the first divisor. Following a predetermined number of division cycles by the selectable first divisor, the reference clock signal is divided a predetermined number of division cycles by a second fixed, or default divisor.
An integrated circuit non-integer counter with selectable divisor is provided for higher edge stability requirements. While completely syncronous, this circuit includes features that significantly reduce power consumption. The non-integer counter uses a high-speed counter, as described above. A load circuit uses only the high-speed counter signal and reference clock signal as inputs, to syncronize the high-speed counter signals.
A generator accepts the load pulse, the reference clock signal, and control signals. Generator outputs provides divisor commands responsive to the control signals, and a generator count signal that is a syncronously divided quotient of the load pulse. As in the partially-syncronous counter, the load pulse initializes the high-speed counter section with divisor commands to enable a selectable first divisor. The overall division ratio of the counter is created by combining division cycles of the first and second divisor.
A partially-syncronous method for dividing a reference clock is also provided that comprises: accepting a reference clock signal; accepting divisor commands to select a first divisor; syncronously dividing the reference clock signal with either the first, or a second divisor; in response to syncronously dividing the reference clock signal, supplying high-speed counter signals; asyncronously dividing the high-speed counter signals; in response to asyncronously dividing the high-speed counter signal, supplying a low-speed counter signal; in response to the high-speed and low-speed counter signals, initializing the high-speed counter signals; and, in response to initializing the high-speed counter signals, accepting the divisor commands.
A non-integer method for dividing a reference clock with a selectable divisor is provided that comprises: accepting a reference clock signal; accepting control signals to select a first divisor; syncronously dividing the reference clock signal with either the first, or a second divisor; in response to syncronously dividing the reference clock signal, supplying high-speed counter signals; in response to high-speed counter signals and the reference clock signals, supplying a load pulse; dividing the load pulse to supply a divide-by-two signal; selecting a divide-by-two signal edge; in response to the divide-by-two edge selection and the control signals, generating a generator count signal; in response to the generator count signal and the control signals, initializing the high-speed counter signals; and, in response to initializing the high-speed counter signals, supplying the divisor commands.